INVESTIGATION OF APB PROTOCOL IN NON-WAIT STATE IN SEMICONDUCTOR CHIP DESIGN
Main Article Content
Abstract
With the rapid development of low-power SoC and embedded systems, efficient peripheral communication protocols have become increasingly important in semiconductor chip design. This study investigates the Advanced Peripheral Bus (APB) protocol in non-wait-state data transmission for low- bandwidth peripheral applications. The research focuses on the operating principles, communication timing, signal structures, and integration characteristics of the APB protocol within the AMBA architecture. Simulation and functional verification were performed using Vivado 2024.2.1 to analyze continuous read/write transactions and signal synchronization behavior. The results demonstrate that the APB protocol provides simple hardware implementation, stable communication timing, low power consumption, and efficient integration with AHB/AXI-based SoC systems, making it suitable for low- power embedded and IoT applications.
Keywords
APB, AMBA, AHB, IP core, AXI.
Article Details
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